Phase Locked Loops (PLLs) can be an integral component of systems that use clocking for various operations. These systems can include microprocessors, wireless/wireline transceivers, and other devices known to those of skill in the art. Generally, PLLs are used to generate an output waveform which has a timing relationship with an input waveform, such as a 1:1 ratio, a 2:1 ratio, and so on. For instance, an input waveform of 60 Hertz could be inputted into a PLL to generate an output waveform of 120 Hertz. Furthermore, there would be a predefined phase relationship between the input wave and the output wave.
One important element of a PLL is a low pass filter, which typically comprises passive elements, such as capacitors and resistors. In a PLL, the voltage on the LPF is used as an input signal to a voltage controlled oscillator (VCO). Therefore, the voltage on the capacitor should remain stable, so that a stable oscillation occurs within the PLL, thereby leading to a stable output frequency.
Often, metal oxide semiconductors (MOSs) can be used as capacitors within a PLL. For instance, the gate and the source, or the gate and the drain, of a MOS can be used within an integrated circuit as the cathode and anode of a capacitor. However, with the rapid advancement of CMOS technology and the resulting reduction of the gate oxide thickness, a regime is being entered wherein the effect of leakage current through the gate dielectric is a problem.
There are two major regimes pertaining to gate leakage in metal-oxide-semiconductor (MOS) devices. These regimes are the Fowler-Nordheim regime and the direct tunneling regime. In the Fowler-Nordheim tunneling regime, which is dominant for thick (greater the 50 angstrom) oxides, the tunneling is a two-step process. In the first phase, in the presence of a large electric field, carriers at the oxide-semiconductor interface are accelerated. This increases the energy of the carriers (the carriers become hot) such that the barrier they encounter is reduced from trapezoidal to triangular. The tunneling current for the Fowler-Nordheim regime is proportional to the below:IαEox2exp(−B[1−(1−qVox/C)1.5/Eox)wherein Eox is the electric field strength across the gate oxide/dielectric, which is dependent on the potential (Vox) across the MOS capacitor, and B is a constant.
In the direct tunneling regime, the oxide is thin enough for carriers to directly tunnel across the trapezoidal barrier. The current in the direct tunnel regime is proportional to the following equation:IαEox2exp(−B[1−(1−qVox/C)1.5/Eox)wherein Eox is the electric field across the gate oxide/dielectric, q is the electric change in coulombs, Vox is the voltage across the capacitor dielectric, and B and C are constants. In both of the above equations, the leakage current is exponentially dependent on the voltage across the capacitor.
Generally, the leakage current through the capacitor is exponentially dependent upon the voltage across, as well as the thickness of, the gate dielectric. That is, as the thickness of the gate dielectric gets smaller, the leakage current increases exponentially. Also, increasing the voltage across the capacitor will result in an exponential increase in leakage current.
One trend in device technology is for thinner gate dielectrics to help achieve higher performance. However, the penalty for this is the associated exponential increase in leakage current.
In a PLL, the effect of capacitance leakage on PLL performance can be most noticeable when the PLL is in the locked state (that is, there is a determined relationship between the input phase and the output phase of the waveforms) and the capacitor is not being charged by either charge pump, what is otherwise referred to as a high Z state. Suppose, just before the PLL locks, the voltage at Node X in FIG. 1 is set to a voltage value V. Once the PLL is locked, the charge pumps are both disconnected, but for stable operation, the voltage at Node X should also remain stable. However, due to gate leakage of the large MOS device which is used as a capacitor, the voltage at Node X decays to ground with a time constant that is determined by the effective resistance associated with the tunneling current as well as the value of the capacitance. In some cases, the low pass filter cap is not too leaky. In other words, the time duration over which the discharging takes place is large enough that the resulting jitter will have most of its spectral components within the PLL loop bandwidth. As a result, this jitter is not filtered out.
One conventional solution to minimize this effect is to add a resistor in parallel with the low pass filter capacitor between Node X of FIG. 1 and electrical ground. If this added resistor has a value smaller than the effective resistance associated with the tunneling current in the filter capacitor, the resulting jitter at Node X will have its spectrum pushed out to higher frequencies. However, the addition of this resistor reduces the effective dominant pole frequency of the PLL, thereby reducing PLL bandwidth. So, one faces the tradeoff of lowered PLL bandwidth with reduced leakage induced jitter.
In the time domain, this resistor can be considered as making the LPF capacitor more leaky, thereby pushing the center of the spectral distribution of the jitter at Node X to a higher frequency, which can subsequently be filtered out. However, while long-term jitter is filtered out, the output of the VCO can suffer from substantial cycle-to-cycle jitter.
Therefore, there is a need to minimize jitter due to leaky filter capacitors that avoids at least some of the trade offs between loop bandwidth and jitter suppression.